Offset pads over tsv

ABSTRACT

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

PRIORITY CLAIM AND CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(e)(1) of U.S.Provisional Application No. 62/684,505, filed Jun. 13, 2018, which ishereby incorporated by reference in its entirety.

FIELD

The following description relates to integrated circuits (“ICs”). Moreparticularly, the following description relates to manufacturing IC diesand wafers.

BACKGROUND

Microelectronic elements often comprise a thin slab of a semiconductormaterial, such as silicon or gallium arsenide, commonly called asemiconductor wafer. A wafer can be formed to include multipleintegrated chips or dies on a surface of the wafer and/or partlyembedded within the wafer. Dies that are separated from a wafer arecommonly provided as individual, prepackaged units. In some packagedesigns, the die is mounted to a substrate or a chip carrier, which isin turn mounted on a circuit panel, such as a printed circuit board(PCB). For example, many dies are provided in packages suitable forsurface mounting.

Packaged semiconductor dies can also be provided in “stacked”arrangements, wherein one package is provided, for example, on a circuitboard or other carrier, and another package is mounted on top of thefirst package. These arrangements can allow a number of different diesor devices to be mounted within a single footprint on a circuit boardand can further facilitate high-speed operation by providing a shortinterconnection between the packages. Often, this interconnect distancecan be only slightly larger than the thickness of the die itself. Forinterconnection to be achieved within a stack of die packages,interconnection structures for mechanical and electrical connection maybe provided on both sides (e.g., faces) of each die package (except forthe topmost package).

Additionally, dies or wafers may be stacked in a three-dimensionalarrangement as part of various microelectronic packaging schemes. Thiscan include stacking a layer of one or more dies, devices, and/or waferson a larger base die, device, wafer, substrate, or the like, stackingmultiple dies or wafers in a vertical or horizontal arrangement, andvarious combinations of both.

Dies or wafers may be bonded in a stacked arrangement using variousbonding techniques, including direct dielectric bonding, non-adhesivetechniques, such as ZiBond® or a hybrid bonding technique, such as DBI®,both available from Invensas Bonding Technologies, Inc. (formerlyZiptronix, Inc.), an Xperi company. The bonding includes a spontaneousprocess that takes place at ambient conditions when two preparedsurfaces are brought together (see for example, U.S. Pat. Nos. 6,864,585and 7,485,968, which are incorporated herein in their entirety).

Respective mating surfaces of the bonded dies or wafers often includeembedded conductive interconnect structures (which may be metal), or thelike. In some examples, the bonding surfaces are arranged and aligned sothat the conductive interconnect structures from the respective surfacesare joined during the bonding. The joined interconnect structures formcontinuous conductive interconnects (for signals, power, etc.) betweenthe stacked dies or wafers.

There can be a variety of challenges to implementing stacked die andwafer arrangements. When bonding stacked dies using a direct bonding orhybrid bonding technique, it is usually desirable that the surfaces ofthe dies to be bonded be extremely flat, smooth, and clean. Forinstance, in general, the surfaces should have a very low variance insurface topology (i.e., nanometer scale variance), so that the surfacescan be closely mated to form a lasting bond.

Double-sided dies can be formed and prepared for stacking and bonding,where both sides of the dies will be bonded to other substrates or dies,such as with multiple die-to-die or die-to-wafer applications. Preparingboth sides of the die includes finishing both surfaces to meetdielectric roughness specifications and metallic layer (e.g., copper,etc.) recess specifications. For instance, conductive interconnectstructures at the bonding surfaces may be slightly recessed, just belowthe insulating material of the bonding surface. The amount of recessbelow the bonding surface may be determined by a dimensional tolerance,specification, or physical limitation of the device or application. Thehybrid surface may be prepared for bonding with another die, wafer, orother substrate using a chemical mechanical polishing (CMP) process, orthe like.

In general, when direct bonding surfaces containing a combination of adielectric layer and one or more metal features (e.g., embeddedconductive interconnect structures) are bonded together, the dielectricsurfaces bond first at lower temperatures and the metal of the featuresexpands afterwards, as the metal is heated during annealing. Theexpansion of the metal can cause the metal from both bonding surfaces tojoin into a unified conductive structure (metal-to-metal bond). Whileboth the substrate and the metal are heated during annealing, thecoefficient of thermal expansion (CTE) of the metal relative to the CTEof the substrate generally dictates that the metal expands much morethan the substrate at a particular temperature (e.g., ˜300 C). Forinstance, the CTE of copper is 16.7, while the CTE of fused silica is0.55, and the CTE of silicon is 2.56.

In some cases, the greater expansion of the metal relative to thesubstrate can be problematic for direct bonding stacked dies or wafers.If a metal pad is positioned over a through-silicon via (TSV), theexpansion of the TSV metal can contribute to the expansion of the padmetal. In some cases, the combined metal expansion can cause localizeddelamination of the bonding surfaces, as the expanding metal rises abovethe bonding surface. For instance, the expanded metal can separate thebonded dielectric surfaces of the stacked dies.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is set forth with reference to the accompanyingfigures. In the figures, the left-most digit(s) of a reference numberidentifies the figure in which the reference number first appears. Theuse of the same reference numbers in different figures indicates similaror identical items.

For this discussion, the devices and systems illustrated in the figuresare shown as having a multiplicity of components. Variousimplementations of devices and/or systems, as described herein, mayinclude fewer components and remain within the scope of the disclosure.Alternatively, other implementations of devices and/or systems mayinclude additional components, or various combinations of the describedcomponents, and remain within the scope of the disclosure.

FIG. 1A shows a cross-section of an example substrate with bonding padsand a TSV.

FIG. 1B shows a top view of the example substrate of FIG. 1A.

FIG. 2 shows a cross-section of two example bonded substrates withbonding pads and TSVs, and example resulting delamination.

FIG. 3 shows a cross-section of an example substrate with a bonding padpositioned offset relative to the TSV, according to an embodiment.

FIG. 4 shows a cross-section of an example substrate with a bonding padpositioned offset relative to the TSV, the bonding pad having an unevensurface, according to an embodiment.

FIG. 5 shows a cross-section of an example substrate with a bonding padpositioned offset relative to the TSV and a recess disposed above theTSV, according to an embodiment.

FIGS. 6-14 show a cross-section of an example substrate with a bondingpad positioned offset relative to a TSV, illustrating an examplebackside process of the substrate, according to an embodiment.

FIG. 15 shows a cross-section of two example bonded substrates with TSVsand offset bonding pads, bonded front to back, according to anembodiment.

FIG. 16 shows a cross-section of two example bonded substrates withTSVs, offset bonding pads, and stress recesses, bonded front to back,according to an embodiment.

FIG. 17 shows a cross-section of two example bonded substrates withTSVs, multiple offset bonding pads, and stress recesses, bonded front toback, according to an embodiment.

FIG. 18 shows a cross-section of two example bonded substrates withTSVs, offset bonding pads, and stress recesses, bonded back to back,according to an embodiment.

FIG. 19 shows a cross-section of two example bonded substrates withTSVs, offset bonding pads, and stress recesses, bonded front to front,according to an embodiment.

FIG. 20 shows a diagram of example TSVs used for heat management of adie, according to various embodiments.

FIG. 21 is a text flow diagram illustrating an example process offorming a microelectronic assembly to reduce or eliminate delaminationof the bonded substrates, according to an embodiment.

SUMMARY

Representative techniques and devices are disclosed, including processsteps for preparing various microelectronic devices for bonding, such asfor direct bonding without adhesive. In various embodiments, techniquesmay be employed to mitigate the potential for delamination due to metalexpansion, particularly when a TSV or a bond pad over a TSV is presentedat the bonding surface of one or both devices to be bonded. For example,in one embodiment, the TSV may extend partially through the substrate ofthe device, and a metal contact pad may be disposed at the bondingsurface offset relative to the TSV. For instance, the contact pad isdisposed so that it does not overlap the TSV. The contract pad may beelectrically coupled to the TSV using one or more conductive traces, orthe like.

In an embodiment where a contact pad is positioned offset relative to aTSV, the offset of the pad avoids the metal expansion of the TSVcombining with the metal expansion of the pad, which can reduce oreliminate delamination that could occur otherwise.

In various implementations, an example process includes embedding afirst through silicon via (TSV) into a first substrate having a firstbonding surface, where the first TSV extends partially through the firstsubstrate, normal to the first bonding surface and is not exposed at thefirst bonding surface. A first metal contact pad is disposed at thefirst bonding surface, offset relative to the first TSV, not overlappingthe first TSV, and extending partially into the first substrate belowthe first bonding surface. The first metal contact pad is electricallycoupled to the first TSV with one or more embedded conductive traces.

In various examples, the contact pad may be selected or formed based ona diameter or a surface area of the first metal contact pad, or apredicted recess for the first metal contact pad. For instance, in anembodiment, the process includes determining a desired recess for thefirst metal contact pad relative to the first bonding surface, to allowfor expansion of the material of the first metal contact pad, based onan estimating, and selecting or forming the first metal contact pad tohave a perimeter shape likely to result in the desired recess when thefirst metal contact pad is planarized. This may include forecasting anamount of recess that is likely to occur in a surface of the first metalcontact pad as a result of the planarizing. In another embodiment, theprocess includes forming the desired recess in a surface of the firstmetal contact pad (prior to bonding), based on the prediction.

In various embodiments, the process includes reducing or eliminatingdelamination of bonded microelectronic components by selecting the firstmetal contact pad and offsetting the first contact pad relative to theTSV.

Additionally or alternatively, the back side of the first substrate mayalso be processed for bonding. One or more insulating layers ofpreselected materials may be deposited on the back side of the firstsubstrate to facilitate proper reveal and planarization of the TSV andform the dielectric surface for bonding when the back side of the firstsubstrate is to be direct bonded.

Further, the first TSV, as well as other TSVs within the first substratemay be used to direct or transfer heat within the first substrate and/oraway from the first substrate. In some implementations, the thermaltransfer TSVs may extend partially or fully through a thickness of thefirst substrate and may include a thermally conductive barrier layer. Insuch examples, barrier layers normally used around the TSVs that tend tobe thermally insulating may be replaced with thermally conductive layersinstead. In various implementations, some TSVs may be used for signaltransfer and thermal transfer.

In an embodiment, a microelectronic assembly comprises a first substrateincluding a first bonding surface with a planarized topography having afirst predetermined maximum surface variance. A first through siliconvia (TSV) is embedded in the first substrate and extends partiallythrough the first substrate. The first TSV extends normal to the firstbonding surface and is not exposed at the first bonding surface.

A first metal contact pad is disposed at the first bonding surface andelectrically coupled to the first TSV. The first metal contact pad isdisposed offset relative to the first TSV, not overlapping the firstTSV, and extends partially into the first substrate below the firstbonding surface. One or more embedded conductive traces electricallycouple the first TSV to the first metal contact pad.

Various implementations and arrangements are discussed with reference toelectrical and electronics components and varied carriers. Whilespecific components (i.e., dies, wafers, integrated circuit (IC) chipdies, substrates, etc.) are mentioned, this is not intended to belimiting, and is for ease of discussion and illustrative convenience.The techniques and devices discussed with reference to a wafer, die,substrate, or the like, are applicable to any type or number ofelectrical components, circuits (e.g., integrated circuits (IC), mixedcircuits, ASICS, memory devices, processors, etc.), groups ofcomponents, packaged components, structures (e.g., wafers, panels,boards, PCBs, etc.), and the like, that may be coupled to interface witheach other, with external circuits, systems, carriers, and the like.Each of these different components, circuits, groups, packages,structures, and the like, can be generically referred to as a“microelectronic component.” For simplicity, unless otherwise specified,components being bonded to another component will be referred to hereinas a “die.”

This summary is not intended to give a full description. Implementationsare explained in more detail below using a plurality of examples.Although various implementations and examples are discussed here andbelow, further implementations and examples may be possible by combiningthe features and elements of individual implementations and examples.

DETAILED DESCRIPTION Overview

Referring to FIG. 1A (showing a cross-sectional profile view) and FIG.1B (showing a top view), patterned metal and oxide layers are frequentlyprovided on a die, wafer, or other substrate (hereinafter “die 102”) asa hybrid bonding, or DBI®, surface layer. A representative device die102 may be formed using various techniques, to include a base substrate104 and one or more insulating or dielectric layers 106. The basesubstrate 104 may be comprised of silicon, germanium, glass, quartz, adielectric surface, direct or indirect gap semiconductor materials orlayers or another suitable material. The insulating layer 106 isdeposited or formed over the substrate 104, and may be comprised of aninorganic dielectric material layer such as oxide, nitride, oxynitride,oxycarbide, carbides, carbonitrides, diamond, diamond like materials,glasses, ceramics, glass-ceramics, and the like.

A bonding surface 108 of the device wafer 102 can include conductivefeatures such as contact pads 110, traces 112, and other interconnectstructures, for example, embedded into the insulating layer 106 andarranged so that the conductive features 110 from respective bondingsurfaces 108 of opposing devices can be mated and joined during bonding,if desired. The joined conductive features 110 can form continuousconductive interconnects (for signals, power, etc.) between stackeddevices.

Damascene processes (or the like) may be used to form the embeddedconductive features 110 in the insulating layer 106. The conductivefeatures 110 may be comprised of metals (e.g., copper, etc.) or otherconductive materials, or combinations of materials, and includestructures, traces, pads, patterns, and so forth. In some examples, abarrier layer may be deposited in the cavities for the conductivefeatures 110 prior to depositing the material of the conductive features110, such that the barrier layer is disposed between the conductivefeatures 110 and the insulating layer 106. The barrier layer may becomprised of tantalum, for example, or another conductive material, toprevent or reduce diffusion of the material of the conductive features110 into the insulating layer 106. After the conductive features 110 areformed, the exposed surface of the device wafer 102, including theinsulating layer 106 and the conductive features 110 can be planarized(e.g., via CMP) to form a flat bonding surface 108.

Forming the bonding surface 108 includes finishing the surface 108 tomeet dielectric roughness specifications and metallic layer (e.g.,copper, etc.) recess specifications, to prepare the surface 108 fordirect bonding. In other words, the bonding surface 108 is formed to beas flat and smooth as possible, with very minimal surface topologyvariance. Various conventional processes, such as chemical mechanicalpolishing (CMP), dry or wet etching, and so forth, may be used toachieve the low surface roughness. These processes provides the flat,smooth surface 108 that results in a reliable bond.

In the case of double-sided dies 102, a patterned metal and insulatinglayer 106 with prepared bonding surfaces 108 may be provided on bothsides of the die 102. The insulating layer 106 is typically highlyplanar (usually to nm-level roughness) with the metal layer (e.g.,embedded conductive features 110) at or recessed just below the bondingsurface 108. The amount of recess below the surface 108 of theinsulating layer 106 is typically determined by a dimensional tolerance,specification, or physical limitation. The bonding surfaces 108 areoften prepared for direct bonding with another die, wafer, or othersubstrate using a chemical-mechanical polishing (CMP) step and/or otherpreparation steps.

Some embedded conductive features or interconnect structures maycomprise metal pads 110 or conductive traces 112 that extend partiallyinto the dielectric substrate 106 below the prepared surface 108. Forinstance, some patterned metal (e.g., copper) features 110 or 112 may beabout 0.5-2 microns thick. The metal of these features 110 or 112 mayexpand as the metal is heated during annealing. Other conductiveinterconnect structures may comprise metal (e.g., copper) throughsilicon vias (TSVs) 114 or the like, that extend normal to the bondingsurface 108, partly or fully through the substrate 102 and include alarger quantity of metal. For instance, a TSV 114 may extend about 50microns, depending on the thickness of the substrate 102. The metal ofthe TSV 114 may also expand when heated. Pads 110 and/or traces 112 mayor may not be electrically coupled to TSVs 114, as shown in FIG. 1A.

Referring to FIG. 2, dies 102 may be direct bonded, for instance,without adhesive to other dies 102 with metal pads 110, traces 112,and/or TSVs 114. If a metal pad 110 is positioned over a TSV 114(overlapping and physically and electrically coupled to the TSV 114),the expansion of the TSV 114 metal can contribute to the expansion ofthe pad 110 metal. In some cases, the combined metal expansion can causelocalized delamination 202 of the bonding surfaces at the location ofthe TSV 114 (or TSV 114/pad 110 combination), as the expanding metalrises above the bonding surface 108. For instance, the expanded metalcan separate the bonded dielectric surfaces 108 of the stacked dies 102.

Example Embodiments

Referring to FIGS. 3-5, in various embodiments, techniques may beemployed to mitigate the potential for delamination due to metalexpansion. For example, in one embodiment, a contact pad 110 may bedisposed on the bonding surface 108, offset relative to the TSV 114 andnot overlapping the TSV 114. The contact pad 110 may be embedded in thedielectric layer 106, extending partially into the dielectric layer 106below the bonding surface 106, and electrically coupled to the TSV 114using a trace 112, or the like. In some embodiments, the size of themetal pad 110 may be selected based on the material of the pad 110, itsthickness, and anticipated recess during CMP processing.

In various implementations, disposing the contact pad 110 offsetrelative to the TSV 114 (e.g., the contact pad 110 is not disposed overthe TSVs 114 or overlapping the TSV 114) reduces or eliminatesdelamination of bonded dies 102, when the dies 102 are heat annealed andthe metal of the TSV 114 and the contact pad 110 expand. In theimplementations, the TSV 114 will not (or is less likely to) contributeits expanding metal to the expanding metal of the offset pad 110.Accordingly, a predetermined recess in the pad 110 can be sufficient toprovide room for the material expansion of the pad 110.

In an embodiment, the size of the contact pads 110 are selected orformed by estimating an amount that the material of the contact pad 110will expand when heated to a preselected temperature (˜300°), based on avolume of the material of the contact pad 110 and a coefficient ofthermal expansion (CTE) of the material of the contact pad 110, andpredicting an amount that the material of the contact pad 110 willexpand when heated to the preselected temperature. The contact pad 110is planarized along with the bonding surface 108 of the dielectric layer106, including recessing the contact pad 110 to have a predeterminedrecess depth (or amount) relative to the bonding surface 108, based onestimating and predicting the expansion of the contact pad 110 materialat the predetermined temperature.

In one embodiment, a contact pad 110 may be selectively etched (via acidetching, plasma oxidation, etc.) to provide the desired recess depth (toaccommodate a predicted metal expansion). In another example, as shownat FIG. 4, a pad 110 or a corresponding TSV 114 may be selected, formed,or processed to have an uneven top surface as an expansion buffer. Forexample, referring to FIG. 4, the top surface of the pad 110 may beformed or selectively etched to be rounded, domed, convex, concave,irregular, or otherwise non-flat to allow additional space 402 formaterial expansion.

The additional space 402 may be determined and formed based on theprediction of the amount that the material of the contact pad 110 willexpand when heated. In various implementations, the top surface of thecontact pad 110 may be formed to be uneven during deposition, or may beetched, grinded, polished, or otherwise made uneven after forming thecontact pad 110. In some cases, the top surface of the pad 110 may bemade uneven during CMP of the bonding surface 108.

Additionally or alternately, the dielectric 106 around the metal pad 110can be formed or shaped to allow room for the metal of the pad 110 toexpand. In one example, a CMP process can be used to shape the surface108 of the dielectric 106 around the metal pad 110, or in other examplesother processes can be used, so that the dielectric 106 around the pad110 includes a recess or other gap that provides room for metalexpansion. In an embodiment, the dielectric 106 can be recessed (e.g.,with CMP) while the bonding surface 108 is being prepared. In theembodiment, the metal pad 110 and the dielectric 106 may be recessedconcurrently (but at different rates). For instance, the process mayform erosion in the dielectric 106 around the edges of the metal pad 110while recessing the metal pad 110.

In various embodiments, the pad 110 and/or the TSV 114 are comprised ofcopper, a copper alloy, or the like. In a further embodiment, thematerials of the pad 110 and/or the TSV 114 may be varied to controlmetal expansion and potential resulting delamination. For instance, insome embodiments, the pad 110 and/or the TSV 114 may be comprised ofdifferent conductive materials, perhaps with lower CTEs. In someembodiments the TSV 114 may be comprised of a different conductivematerial (with a lower CTE) than the contact pad 110. For example, theTSV 114 may be comprised of tungsten, an alloy, or the like.

In other embodiments the volume of material of the TSV 114 may be variedto control metal expansion and the potential for resulting delamination.For instance, in some embodiments, a TSV 114 with a preselected materialvolume (e.g., less volume of material) may be used, when this isallowable within the design specifications. The preselection of volumeof the TSV 114 may be based on predicted material expansion of the TSV114.

Alternately, the top surface of the TSV 114 can be arranged to beexposed at the bonding surface 108 and used as a contact pad. Thisarrangement can avoid combining the expansion of the metal pad 110 withthat of the TSV 114, and so minimize or eliminate delamination.

In another implementation, as shown at FIG. 5, a recess 502 is disposedin the bonding surface 108 and through a portion of the insulating layer106 to provide stress relief for material expansion of the TSV 114 inthe z-direction. For instance, the recess 502 can be formed by etchingthe dialectic layer 106. In the implementation, at least a portion ofthe recess 502 is disposed over (e.g., overlapping) the TSV 114. Therecess 502 can be tuned, for example, to the volume of the TSV 114,using a prediction of the expansion of the TSV 114, based on the volumeof the particular metal of the TSV 114. In some cases, the diameter orarea of the recess 502 is larger than the diameter or cross-sectionalarea of the TSV 114.

The recess 502 may or may not expose the TSV 114. The recess 502 mayhave a depth that extends to the top of the TSV 114 or the trace 112(for instance if it was desired to make contact with the TSV 114 or thetrace 112), but generally the depth of the recess 502 is more shallowand the TSV 114 and/or the trace 112 remain covered by a portion of theinsulating layer 106. The recess 502 may be left open or may be filledwith a material, such as a compliant material.

After preparation of the bonding surface 108 (e.g., by CMP) the die 102may be direct bonded, for instance, without adhesive to other dies 102with metal pads 110, traces 112, and/or TSVs 114. The material of theTSV 114 and the material of the pad 110 expand during heated annealingas the mating contact pads 110 of opposite dies 102 bond to form asingle conductive interconnect. However, the metal expansion does notcause delamination of the bonding surfaces since the expanding metal ofthe TSV 114 does not combine with the expanding metal of the contactpads 110 (because the contact pads 110 are offset from the TSVs 114).

Further, if the contact pads 110 are sufficiently recessed, theexpanding metal of the contact pads 110 does not separate the bondeddielectric surfaces 108 of the stacked dies 102 (see FIGS. 15-19). Whenusing surface preparation processes such as CMP to prepare the bondingsurface 108 of the die 102, the metal pads 110 on the bonding surface108 can become recessed (intentionally or unintentionally) relative tothe dielectric 106, due to the softness of the contact pads 110 (whichmay comprise copper, for instance) relative to the dielectric 106 (whichmay comprise an oxide, for example).

In various embodiments, the amount of recessing of a metal pad 110 maybe predictable, based on the surface preparation technique used (e.g.,the chemical combination used, the speed of the polishing equipment,etc.), the materials of the dielectric layer 106 and the metal pads 110,the spacing or density of the metal pads 110, and the size (e.g., areaor diameter) of the metal pads 110. In the embodiments, the area ordiameter of the metal pads 110 may be selected (e.g., for a particularmetal thickness) to avoid delamination of bonded dies 102 based on therecess prediction and the expected metal expansion of the metal pad 110.

In the embodiments, the shape and size of a contact pad 110 positionedoffset from a TSV 114 may be tailored or selected to avoid delaminationbased on the recess prediction and the expected metal expansion of themetal pad 110.

Additional Embodiments

FIGS. 6-14 illustrate examples of backside die 102 processing, accordingto various embodiments. In some implementations, where dies 102 arestacked and direct bonded without adhesive, the backside 602 of the die102 may receive different preparation than the topside bonding surface108, when the backside 602 is prepared for direct bonding. Instead offorming the dielectric layer 106 on the backside 602 of the die 102, thebackside 602 may be prepared differently to reduce process steps, reducemanufacturing costs, or for other reasons.

In one implementation, the backside 602 is prepared so that the TSV 114is exposed, to be used as a contact surface for bonding to a conductivepad, interconnect, or other conductive bonding surface. The preparationmay include depositing one or more layers of insulating material andplanarizing (via CMP, for example) the insulating material to reveal theTSV 114. In some cases, however, the expansion of the material of theTSV 114 during heated annealing can cause the insulating material and/orthe substrate 104 to become damaged.

In an embodiment, as shown in FIGS. 6-14, one or more layers ofinorganic dielectric materials with different residue stresscharacteristics may be deposited on the backside 602 to balance stresson the device side of the die 102 and minimize die warpage aftersingulation. The layers of insulating material can be planarized andotherwise prepared as a bonding surface on the backside 602 of the die102.

As shown at FIG. 6, the TSV 114 is disposed within the die 102,transverse to the bonding surface 108 of the die 102. A dielectric linerand diffusion barrier 604 surrounds the TSV 114 to prevent diffusion ofthe metal of the TSV 114 (e.g., copper) into the material of the basesubstrate 104 (e.g., silicon). The base substrate 104 is thinned andselectively etched to expose the bottom end of the TSV 114 with theliner and diffusion barrier layer 604 intact. In an embodiment, as shownat FIG. 6, another diffusion barrier 606 is deposited on the surface ofthe backside 602 of the die 102. In an example, the diffusion barrier606 comprises a dielectric, such as a nitride or the like.

In various embodiments, one or more dielectric layers, which may havedifferent residue stress characteristics are then deposited onto thebackside 602 of the die 102 to prevent damage to the die 102 when thematerial of the TSV 114 expands. For example, a first layer 608,comprising a first low temperature dielectric, such as an oxide, may bedeposited over the backside 602, including over the diffusion layer 606.FIG. 7 shows this scenario with a formed contact pad 110 on the frontside bonding surface 108.

As shown at FIG. 8, the backside 602 is planarized (via CMP, forexample), including the one or more dielectric layers 608 to form aflat, smooth bonding surface for direct bonding. The remainingdielectric layer 608 can assist with warpage control, based on a residuestress characteristic of the dielectric layer 608.

In an embodiment, as shown at FIGS. 9-10, a contact pad 1004 (or otherconductive structure) may be coupled to the TSV 114 on the backside 602of the die 102. As shown at FIG. 9, after deposition of the first lowtemperature oxide stress layer 608 (which also comprises the bondinglayer in some implementations), a second dielectric layer 902 (which maycomprise a low temperature oxide) may be deposited over the first layer608. No barrier or adhesion layer is needed between the two oxide layers(608 and 902). In various implementations, the first layer 608 and thesecond layer 902 are comprised of similar or the same materials (invarying thicknesses). In other implementations, the first layer 608 andthe second layer 902 are comprised of different materials. In alternateimplementations, additional dielectric layers may also be deposited overthe first 608 and second 902 layers.

The backside 602 is patterned and opened (e.g., etched, etc.) fordeposition of a conductive pad 1004. As shown at FIG. 9, the opening 904in the oxide layers 608 and 902 may have a different shape than that ofthe TSV 114. (The opening for an RDL layer is most likely to be a line,not a circle)

In an embodiment, the opening 904 for the conductive pad 1004 extendsthrough the second layer 902 and partially (10-1000 nm) into the firstlayer 608. A barrier/adhesion layer 1002 (comprising titanium/titaniumnitride, tantalum/tantalum nitride, etc.) may be deposited into theopening 904 (and may cover the entire surface of the opening 904), asshown at FIG. 10. A copper (or the like) deposition/plating (e.g.,damascene process) fills the opening 904, which is planarized (via CMP,for example) to remove excess copper and to set a recess of theresulting conductive pad 1004 to a specified depth. The backside 602surface may be prepared for bonding at this point. Alternately, a dualdamascene process may be used to form an interconnect such as theconductive structure 1004, as desired.

In another embodiment, as shown at FIG. 11, a thin (˜10-500 nm) adhesionlayer 1102, which may comprise silicon nitride, or the like, isdeposited over the surface of the backside 602 (e.g., over the secondlayer 902 and the conductive pad 1004), followed by a third dielectriclayer 1104 (e.g., oxide) as a bonding layer (e.g., DBI layer) for thebackside 602. A thickness of the third dielectric layer 1104 (top layer)and a thickness of the conductive pad 1004 may be adjusted to minimizethin die warpage, and to achieve a desired anneal temperature. Invarious implementations, the first layer 608, the second layer 902, andthe third layer 1104 are comprised of similar or the same materials (invarying thicknesses). In other implementations, one or more of the firstlayer 608, the second layer 902, and/or the third layer 1104 arecomprised of different materials. In alternate implementations,additional dielectric layers may also be deposited over the first 608,second 610, and third 1104 layers to balance stress on the device sideand minimize die warpage.

As shown at FIG. 12, the third layer 1104 may be patterned and etchedfor pad 1204 deposition. After etching an opening in the third layer1104, a diffusion/adhesion layer 1202 (e.g., Ti/TiN) may be deposited toline the opening, after which the opening is filled (via damasceneprocess, for example) with conductive material (e.g., copper) to formthe pad 1204. The pad 1204 and the third layer 1104 are planarized(using CMP, for example) to prepare the backside 602 for direct bondingand to recess the pad 1204 to specification. In an alternate embodiment,as shown at FIG. 13, a dual damascene process may be used to add the pad1204 as part of a via layer 1302.

In an implementation, as shown at FIG. 14, a recess 1402 can be etchedon the backside 602 over the TSV 114, as a stress relief for metalexpansion during annealing. The recess 1402 is disposed in the surfaceof the third layer 1104 (or other top-last layer of the backside 602)and through a portion of the third layer 1104 to provide stress relieffor material expansion of the TSV 114 in the -z-direction. In theimplementation, at least a portion of the recess 1402 is disposed over(e.g., overlapping) the TSV 114. The recess 1402 can be tuned, forexample, to the volume of the TSV 114, using a prediction of materialexpansion of the TSV 114, based on the volume of the particular metal ofthe TSV 114. In some cases, the diameter or area of the recess 1402 islarger than the diameter or cross-sectional area of the TSV 114. Therecess 1402 may be left open or may be filled with a material, such as acompliant material.

In other embodiments, alternate techniques may be used to reduce oreliminate delamination due to metal feature expansion, and remain withinthe scope of the disclosure.

FIGS. 15-19 show example stacking arrangements of the dies 102 formedwith regard to FIGS. 6-14 (and like structures) with front side 108 andbackside 602 interconnectivity. For example, at FIG. 15, an example“front-to-back” die 102 stack arrangement is shown. This bonds a frontside bonding surface 108 of a first die 102 to a backside 602 bondingsurface of a second die 102, including a contact pad 110 of the firstdie 102 to a contact pad 1204 of the second die 102. In an example, asdiscussed above, the conductive structure 1004 of the first and seconddies 102 penetrate into the second dielectric layer 902 and the firstdielectric layer 608 (without going through the first dielectric layer608) of the first and second dies 102, below the respective bondingsurfaces 602.

At FIG. 16, another example “front-to-back” die 102 stack arrangement isshown. In the embodiment illustrated at FIG. 16, each die 102 includes arecess 1402 at the backside 602 of the die 102, through the topmostlayer (in this example, the third layer 1104). As discussed above, therecess 1402 provides stress relief from expanding material of the TSVs114 during heated annealing. In an implementation, the recess 1402 maybe filled with a compliant material. In an example, as discussed above,the conductive structure 1004 of the first and second dies 102 penetrateinto the second dielectric layer 902 and the first dielectric layer 608(without going through the first dielectric layer 608) of the first andsecond dies 102, below the respective bonding surfaces 602.

At FIG. 17, a further example “front-to-back” die 102 stack arrangementis shown. In the embodiment illustrated at FIG. 17, each die 102includes multiple contact pads 110 (which may be coupled to therespective TSV 114 by one or more traces 112, or the like) and multiplecontact pads 1204 (which may be coupled to the respective TSV 114 by aconductive structure 1004, or the like). The first and second dies 102are stacked so that the multiple contact pads 110 of the first die 102are bonded to the multiple contact pads 1204 of the second die 102.

In various implementations, the dies 102 may include a recess 1402disposed on the backside 602 above the respective TSV 114 (as shown inFIG. 17) to provide stress relief from expanding material of the TSVs114 during heated annealing. In an implementation, the recesses 1402 maybe filled with a compliant material. In an example, as discussed above,the conductive structure 1004 of the first and second dies 102 penetrateinto the second dielectric layer 902 and the first dielectric layer 608(without going through the first dielectric layer 608) of the first andsecond dies 102, below the respective bonding surfaces 602.

At FIG. 18, an example “back-to-back” die 102 stack arrangement isshown. This bonds a backside 602 bonding surface of a first die 102 to abackside 602 bonding surface of a second die 102, including a contactpad 1204 of the first die 102 to a contact pad 1204 of the second die102. In an example, as discussed above, the conductive structure 1004 ofthe first and second dies 102 penetrate into the second dielectric layer902 and the first dielectric layer 608 (without going through the firstdielectric layer 608) of the first and second dies 102, below therespective bonding surfaces 602.

At FIG. 19, an example “front-to-front” die 102 stack arrangement isshown. This bonds a front side bonding surface 108 of a first die 102 toa front side bonding surface 108 of a second die 102, including one ormore contact pads 110 of the first die 102 to one or more contact pads110 of the second die 102. In the example shown, the contact pads 110are electrically coupled to the TSVs 114 of the respective dies 102 byone or more traces 112, or the like. In an example, as discussed above,the conductive structure 1004 of the first and second dies 102 penetrateinto the second dielectric layer 902 and the first dielectric layer 608(without going through the first dielectric layer 608) of the first andsecond dies 102, below the respective bonding surfaces 602.

In various embodiments, as illustrated at FIG. 20, one or more of theTSVs 114 of a set of stacked dies 102 may be used to conduct heat inaddition to or instead of electrical signals. For example, in somecases, it may not be practical or possible to attach a heat sink (orother heat transfer device) to a die 102 of a set of stacked dies 102 toalleviate heat generated by the die 102. In such cases, other techniquesmay be looked-for to transfer heat as desired.

In the embodiments, as shown at FIG. 20, various configurations of TSVs114, including TSVs that extend partially or fully through a die 102,may be employed to conduct heat away from the dies 102 (or away from aheat-generating portion of the dies 102). The TSVs 114 of one die 102may be used in conjunction with TSVs 114, contact pads 110, traces 112,and the like, of the second die 102 to complete heat transfer from onedie 102 to the other die 102, and so forth. The TSVs 114 of the firstdie 102 can be direct bonded (e.g., DBI) to the TSVs 114, contact pads110, traces 112, and the like of the second die 102 for high performancethermal conductivity.

In an implementation, some of the TSVs 114, contact pads 110, traces112, and the like are electrically floating or “dummy” structures, whichcan be used for thermal transfer. These structures may conduct heat awayfrom a high power die 102 to another die 102 or substrate as desired.Dummy contact pads 110 may be coupled to via last or via mid thermalTSVs 114 for thermal conduction.

In the embodiments, diffusion barrier layers 604, which surround theTSVs 114 and can be thermally restrictive or thermal barriers may bereplaced by diffusion barriers of a different material having somethermal conductivity (such as metal or alloy barriers, or the like).

Example Process

FIG. 21 illustrates a representative process 2100 for preparing variousmicroelectronic components (such as dies 102, for example) for bonding,such as for direct bonding without adhesive, while reducing oreliminating the potential for delamination due to metal expansion ofembedded structures at the bonding surface. For instance,through-silicon vias (TSVs) at the bonding surface may causedelamination, particularly when coupled to contact pads, as the materialof the TSVs and the contact pads expands during heated annealing. Theprocess refers to FIGS. 1-20.

The order in which the process is described is not intended to beconstrued as limiting, and any number of the described process blocks inthe process can be combined in any order to implement the process, oralternate processes. Additionally, individual blocks may be deleted fromthe process without departing from the spirit and scope of the subjectmatter described herein. Furthermore, the process can be implemented inany suitable hardware, software, firmware, or a combination thereof,without departing from the scope of the subject matter described herein.In alternate implementations, other techniques may be included in theprocess in various combinations and remain within the scope of thedisclosure.

In an implementation, a die, wafer, or other substrate (a “substrate”)is formed using various techniques to include a base substrate and oneor more dielectric layers. In the implementation, at block 2102, theprocess 2100 includes embedding a first through silicon via (TSV) (suchas TSV 114, for example) into a first substrate having a first bondingsurface (such as bonding surface 108, for example), the first TSVextending partially through the first substrate, normal to the firstbonding surface and not exposed at the first bonding surface.

In the implementation, at block 2104, the process includes disposing afirst metal contact pad (such as contact pad 110, for example) at thefirst bonding surface, offset relative to the first TSV, not overlappingthe first TSV, and extending partially into the first substrate belowthe first bonding surface. In an implementation, the process includespredicting an amount that a material of the first metal contact pad willexpand when heated to a preselected temperature, based on a volume ofthe material of the first metal contact pad and a CTE of the material ofthe first metal contact pad; and selecting the first metal contact padbased on the predicting. In an example, the selecting comprisesselecting a diameter or a surface area of the first metal contact pad.

In another example, the process includes determining a desired recessfor the first metal contact pad relative to the first bonding surface,to allow for expansion of the material of the first metal contact pad;and selecting the first metal contact pad to have a perimeter shapelikely to result in the desired recess when the first metal contact padis planarized. In an embodiment, the process includes forecasting anamount of recess that is likely to occur in a surface of the first metalcontact pad as a result of the planarizing, based on a diameter or anarea of the first metal contact pad, and selecting the first metalcontact pad based on the forecasting.

In an implementation, the process includes determining a desired recessfor the first metal contact pad relative to the first bonding surface,to allow for expansion of the material of the first metal contact pad;and forming the desired recess in a surface of the first metal contactpad. In one example, the process includes forming the surface of thefirst metal contact pad to have a domed or uneven topology.

At block 2106, the process includes electrically coupling the firstmetal contact pad to the first TSV with one or more embedded conductivetraces (such as conductive traces 112, for example).

In an implementation, the process includes planarizing the first bondingsurface to have a predetermined maximum surface variance for directbonding and the first metal contact pad to have a predetermined recessrelative to the first bonding surface.

In an implementation, the process includes forming a recess (such as therecess 502, for example) in the first bonding surface above the firstTSV. In one example, the process includes estimating an amount that amaterial of the first TSV will expand when heated to a preselectedtemperature, based on a volume of the material of the first TSV and acoefficient of thermal expansion (CTE) of the material of the first TSV;and determining a depth and an area of the recess in the first bondingsurface, based on the volume of the material of the first TSV and acoefficient of thermal expansion (CTE) of the material of the first TSV.For instance, the process can include forming the recess in the firstbonding surface to have a diameter that is larger by a predeterminedamount than a diameter of the first TSV.

In an implementation, the process includes depositing one or moreinsulating stress-relief layers on a second surface of the firstsubstrate opposite the insulating layer and planarizing the one or morestress-relief layers to form a second bonding surface having a secondpredetermined maximum surface variance. In an example, the processincludes depositing a first low temperature insulating layer at thesecond surface of the first substrate, a second low temperatureinsulating layer over the first low temperature insulating layer, and athird insulating layer over the second low temperature insulating layerto form the second bonding surface.

In an implementation, the process includes patterning the second lowtemperature insulating layer, etching an opening over the first TSV, theopening extending through the second low temperature insulating layerand partially through the first low temperature insulating layer,depositing a conductive material within the opening to form a conductivepad electrically coupled to the first TSV, and depositing the thirdinsulating layer over the second low temperature insulating layer andthe conductive pad. In an example, the process includes depositing abarrier layer onto exposed surfaces of the opening prior to depositingthe conductive material within the opening.

In another implementation, the process includes patterning the thirdinsulating layer, etching a second opening over the conductive pad, thesecond opening extending through the third insulating layer and exposingthe conductive pad, and depositing a conductive material within thesecond opening to form a second contact pad electrically coupled to theconductive pad.

In an implementation, the process includes direct bonding the firstsubstrate to a second substrate using a direct dielectric-to-dielectric,non-adhesive bonding technique at the second bonding surface of thefirst substrate or at the first bonding surface of the first substrate.

In an alternate implementation, the process includes transferring heatfrom the first substrate to the second substrate via the first TSV andone or more conductive structures embedded within the second substrateand exposed at a bonding surface of the second substrate.

In various embodiments, some process steps may be modified oreliminated, in comparison to the process steps described herein.

The techniques, components, and devices described herein are not limitedto the illustrations of FIGS. 1-21, and may be applied to other designs,types, arrangements, and constructions including with other electricalcomponents without departing from the scope of the disclosure. In somecases, additional or alternative components, techniques, sequences, orprocesses may be used to implement the techniques described herein.Further, the components and/or techniques may be arranged and/orcombined in various combinations, while resulting in similar orapproximately identical results.

Conclusion

Although the implementations of the disclosure have been described inlanguage specific to structural features and/or methodological acts, itis to be understood that the implementations are not necessarily limitedto the specific features or acts described. Rather, the specificfeatures and acts are disclosed as representative forms of implementingexample devices and techniques.

What is claimed is:
 1. A method of forming a microelectronic assembly,comprising: providing a first through silicon via (TSV) into a firstsubstrate having a first bonding surface, the first TSV extending in adirection from the first surface through at least a portion of the firstsubstrate; providing recesses in the bonding layer, wherein at least onefirst recess is aligned with the TSV in a direction normal to the firstsurface and at least one second recess is offset and not overlapping theTSV in the direction normal to the first surface; and disposing a firstmetal contact pad in the second recess, the first metal contact pad ator slightly recessed from the first bonding surface, the first metalcontact pad electrically coupled to the first TSV with one or moreembedded conductive traces.
 2. The method of forming a microelectronicassembly of claim 1, wherein the traces are provided as part of aredistribution layer and at least a portion of the redistribution layeris between the first TSV and first recess.
 3. The method of forming amicroelectronic assembly of claim 2, wherein the first recesscompensates for the expansion of the conductive via during a bondingprocess.
 4. The method of forming a microelectronic assembly of claim 2,further comprising forming the recess in the first bonding surface tohave a diameter that is larger by a predetermined amount than a diameterof the first TSV.
 5. The method of forming a microelectronic assembly ofclaim 1, further comprising shaping the surface of the first metalcontact pad.
 6. The method of forming a microelectronic assembly ofclaim 1, further comprising removing material from the first substrateto expose the TSV from the side opposite the first bonding surface. 7.The method of forming a microelectronic assembly of claim 1, furthercomprising bonding the first substrate to a second substrate, the firstrecess adjacent to a bonding interface between the first and secondsubstrates.
 8. A method of forming a microelectronic assembly,comprising: forming a first substrate to have a base layer and aninsulating layer over the base layer, the insulating layer having afirst bonding surface, a first through silicon via (TSV) extending atleast partially through the base layer of the first substrate in adirection normal to the first bonding surface; forming a recess in thefirst bonding surface overlapping the first TSV, the recess configuredto compensate for thermal expansion of the TSV during a bonding step;disposing a first metal contact pad at the first bonding surface, thefirst metal contact pad offset relative to a location of the first TSV;and electrically coupling the first metal contact pad to the first TSVwith one or more embedded conductive traces.
 9. The method of forming amicroelectronic assembly of claim 8, further comprising planarizing thefirst bonding surface to have a predetermined maximum surface variancefor direct bonding and the first metal contact pad to have apredetermined recess relative to the first bonding surface.
 10. Themethod of forming a microelectronic assembly of claim 8, furthercomprising depositing one or more inorganic dielectric layers on asecond surface of the first substrate opposite the insulating layer andplanarizing the one or more inorganic dielectric layers to form a secondbonding surface having a second predetermined maximum surface variance.11. The method of forming a microelectronic assembly of claim 10,wherein the depositing comprises depositing a first low temperatureinsulating layer at the second surface of the first substrate, a secondlow temperature insulating layer over the first low temperatureinsulating layer, and a third insulating layer over the second lowtemperature insulating layer to form the second bonding surface.
 12. Themethod of forming a microelectronic assembly of claim 11, furthercomprising: patterning the second low temperature insulating layer;etching an opening over the first TSV, the opening extending through thesecond low temperature insulating layer and partially through the firstlow temperature insulating layer; and depositing a conductive materialwithin the opening to form a conductive pad electrically coupled to thefirst TSV; forming a recess in or above the conductive material relativeto the second bonding layer.
 13. The method of forming a microelectronicassembly of claim 12, further comprising depositing an adhesion/barrierlayer onto exposed surfaces of the opening prior to depositing theconductive material within the opening.
 14. The method of forming amicroelectronic assembly of claim 14, further comprising direct bondingthe first substrate to a second substrate using a directdielectric-to-dielectric, non-adhesive bonding technique at the secondbonding surface of the first substrate.
 15. The method of forming amicroelectronic assembly of claim 14, further comprising direct bondingthe first substrate to a second substrate using a directdielectric-to-dielectric, non-adhesive bonding technique at the firstbonding surface of the first substrate.
 16. A microelectronic assembly,comprising: a first substrate including a first bonding surface with aplanarized topography having a first predetermined maximum surfacevariance; a first through silicon via (TSV) embedded in the firstsubstrate and extending at least partially through the first substrate,the first TSV extending normal to the first bonding surface and notexposed at the first bonding surface; a first metal contact pad disposedat the first bonding surface and electrically coupled to the first TSV,the first metal contact pad disposed offset relative to the first TSV,not overlapping the first TSV, and extending partially into the firstsubstrate below the first bonding surface; and one or more embeddedconductive traces electrically coupling the first TSV to the first metalcontact pad.
 17. The microelectronic assembly of claim 16, furthercomprising a recess in the first bonding surface above the first TSV.18. The microelectronic assembly of claim 16, further comprising one ormore dielectric stress-relief layers on a second surface of the firstsubstrate, the one or more stress-relief layers planarized to form asecond bonding surface having a second predetermined maximum surfacevariance.
 19. The microelectronic assembly of claim 18, the one or morestress-relief layers comprising a first low temperature insulating layerat the second surface of the first substrate, a second low temperatureinsulating layer over the first low temperature insulating layer, and athird insulating layer over the second low temperature insulating layerto form the second bonding surface.
 20. The microelectronic assembly ofclaim 16, further comprising a second substrate direct bonded to thefirst substrate using a direct dielectric-to-dielectric, non-adhesivebonding technique at the first bonding surface of the first substrate orat a second bonding surface of the first substrate,.